📚 Course Overview
This comprehensive course covers computer organization, instruction set architecture, processor design, memory systems, and I/O systems with emphasis on the RISC-V architecture.
- Computer Organization & Architecture
- RISC-V Instruction Set Architecture
- Processor Design & Implementation
- Memory Hierarchy & Cache Systems
- I/O Systems & Peripherals
- Parallel Processing & Performance
🎯 Learning Objectives
By the end of this course, you will be able to:
- Understand computer organization principles
- Design and implement basic processors
- Analyze memory system performance
- Program in RISC-V assembly language
- Evaluate computer system performance
- Design cache and memory hierarchies
🔬 Laboratory Work
Hands-on experience with processor design and simulation:
- RISC-V Assembly Programming
- Single-Cycle Processor Design
- Pipelined Processor Implementation
- Cache Memory Simulation
- Performance Analysis & Optimization
- FPGA Implementation Projects
- Verilog Hardware Description
📊 Assessment Structure
Your understanding will be evaluated through:
- Laboratory Assignments (30%)
- Design Projects (25%)
- Mid-term Examination (20%)
- Final Comprehensive Exam (20%)
- Quizzes & Participation (5%)
🛠️ Tools & Simulators
Industry-standard design and simulation tools:
- RISC-V Simulator & Assembler
- Logisim Digital Circuit Designer
- Verilog Hardware Description Language
- ModelSim FPGA Simulator
- Performance Analysis Tools
- Cache Simulation Software
📖 Reference Materials
- Computer Organization and Design by Patterson & Hennessy
- Computer Architecture: A Quantitative Approach
- RISC-V Reader: An Open Architecture Atlas
- Digital Design and Computer Architecture
- Structured Computer Organization by Tanenbaum
🚀 RISC-V Assembly Example
Simple RISC-V program demonstrating basic operations
# RISC-V Assembly: Calculate factorial of 5
.data
n: .word 5
result: .word 0
.text
.globl _start
_start:
# Load n into register a0
la x5, n
lw a0, 0(x5)
# Call factorial function
jal ra, factorial
# Store result
la x5, result
sw a0, 0(x5)
# Exit program
li a7, 10
ecall
factorial:
# Base case: if n <= 1, return 1
li x6, 1
ble a0, x6, base_case
# Recursive case: n * factorial(n-1)
addi sp, sp, -8
sw ra, 4(sp)
sw a0, 0(sp)
addi a0, a0, -1
jal ra, factorial
lw x5, 0(sp)
lw ra, 4(sp)
addi sp, sp, 8
mul a0, a0, x5
jr ra
base_case:
li a0, 1
jr ra